1. Field of the Invention
The present invention generally relates to testing devices, and more particularly to an improved test pattern generator for generating test vectors in an automatic test pattern generator.
2. Discussion of the Related Art
A variety of automatic test equipment (ATE) has long been known for testing electronic circuits, devices, and other semiconductor and electronic products. Generally, automatic test equipment is divided into two broad categories, analog testers and digital testers. As the names imply, analog testers are generally designed for testing analog circuit devices, while digital testers are designed for testing digital circuit devices. Digital testers, as is known, generally include a testing device having a number of internal circuit cards or channels that, generate programmably controlled test signals for testing and evaluating a Device Under Test (DUT). More specifically, ATE are programmably controlled to be adapted or configured to testing a variety of devices in a variety of ways. This is achieved by programming ATE inputs to inject a certain signal (or signal transition) and by programming ATE outputs to compare a value to a certain pin or signal line on a DUT. In this regard, a digital tester generally includes a test head whereby electrical signals are input to and output from the tester. The test head comprises a number of connectors, each defining a channel, which may be connected via cable or otherwise to a device under test. The electronics within the digital tester may then input and output signals to/from a DUT via the test head.
By way of an extremely simple illustration, consider a digital tester that is configured to test a package containing, among other things, a two input AND gate. The digital tester may be configured to apply a logic one on the two signal lines that correspond to the inputs of the AND gate, then receive the signal on the signal line corresponding to the output to ensure that it is driven to a logic one in response. The tester may then be configured to alternatively apply logic zero signals on each of the two signal lines corresponding to the AND gate inputs, in order to verify that the output of the AND gate transitions from a logic one to a logic zero in response. If proper (i.e., expected) operation is not realized then a defect is detected.
An integrated circuit tester includes a set of modules or “nodes”, wherein one node is associated with each terminal of the DUT. When the DUT is an integrated circuit chip (IC) chip, then one node is associated with each pin of the IC chip. A test is organized into a set of successive time segments (“test cycles”). During any given test cycle, each node can either transmit a test signal to the pin, sample a DUT output signal at the associated pin, or do neither. Each node includes its own memory for storing a sequence of these transmit or sample commands (“test vectors”).
As is known by those skilled in the art, a test generator is independent and distinct from a tester. A test generator uses a model of a device to formulate a set of test vectors that will efficiently test for and detect faults on the tested device. Whereas, a tester is a device disposed downstream of the test generator. It utilizes the set of test vectors generated by the test generator in order to test the actual device.
A test vector or test pattern, as generated by a test generator, is a string of n logic values (0, 1, or don't care—X) that are applied to the n corresponding primary inputs (PIs) and/or scan input (SI) logic values of a circuit at the same time frame, usually accompanied by m primary outputs (POs) and/or scan output (SO) logic values that represent the expected circuit response. A test sequence is a series of test vectors applied to a circuit (typically a sequential circuit) in a specific order to detect a target fault. The first vector in the test sequence assumes the circuit to be in a completely unknown state. A test set is an unordered set of test vectors (for combinational circuits) or test sequences (for sequential circuits). For combinational circuits with combinational faults, there is no need for test sequences and the test set consists of an unordered set of test vectors. Stated another way, combinational circuits are tested with test sets containing degenerate test sequences that contain only one test pattern each. Test length refers to the number of test vectors in a test set.
In order to reduce the length of a test set, the test set is often compacted. Traditionally, test set compaction was performed statically. Static compaction is the process of reducing the depth of a test set, after all test vectors have been generated. A circuit to be tested may be modeled, and a fault list for that circuit generated. A “fault” is simply a location where a defect might be manifested. Thus, a fault list, is a listing of many (possibly all) locations where faults may occur. A test vector for each fault from the fault list may be generated to test the given fault. In this way, a single test vector is created to test a given circuit fault.
In early systems, a test set of single-fault test vectors was compacted statically. In this regard, a test vector was created for each and every fault on the fault list. After the entire test set was composed, the depth of the test set was reduced by algorithmic operation. Although the specific algorithm may vary from system to system, the general operation was the same. For example, one known algorithm operated by evaluating the first test vector, and determining whether the second test vector could be compacted with it (the first vector). Then the next test vector was analyzed to determine whether it could be compacted with the first vector, and so on down the vectors of the test set, until the end of the set was reached. Then, the process was repeated for the second test vector. Once a subsequent vector was added to (compacted with) a prior test vector, then the latter test vector was deleted from the test set, thereby reducing its depth by one. This process was completed until a fully compacted test set was obtained.
A paper by Prabhakar Goel and Barry C. Rosales (of IBM Corporation), entitled Test Generation & Dynamic Compaction of Tests, and published in the 1979 IEEE Test Conference (hereafter referred to as “the Goel Paper”), described the advantage of dynamic compaction over static compaction, and is hereby incorporated by reference. In short, static compaction is characterized as a “postprocessing” operation, whereby a set of test vectors are first generated. Each test vector in the list is uniquely defined to test for a given fault in a DUT. Once the set of test vectors is generated, it is processed (ergo postprocessing) to reduce the number of vectors in the set through compaction techniques.
In contrast, dynamic compaction operates to generate compacted vectors one at a time. More specifically, a first test vector is generated to test for a given fault in a list of faults to be tested just like the first test vector generated in static compaction). However, before generating a second test vector, an attempt is made to utilize the first test vector to test for additional faults. In this regard, the unspecified bit positions (i.e., don't care values) may be set to either “1”s or “0”s, or existing bit positions may be utilized, to the extent that the values need not be changed. Although the term dynamic compaction may be somewhat misleading, in that the process does not actually “compact” two existing test vectors, the net result is much the same.
A fully compacted test vector is one wherein (i) no PI is at X (don't care), or (ii) no new faults may be detected by making any X value a 0 or a 1. Ideally, dynamic compaction operates to generate a fully compacted test vector before proceeding to the generation of the next test vector. However, in practice, this is usually not the result. Instead, most dynamic compaction algorithms generate what may be termed “substantially compacted” test vectors. As is known, the degree to which a test vector may be compacted will necessarily depend upon the model for the DUT, as well as the particular vectors that are necessary to generate the needed fault tests. Further, after a certain level of compaction has been obtained, further compaction is extremely computationally intensive and thus time consuming. Therefore, once a certain level of compaction has been obtained, the vector is often deemed substantially compacted, and no further compaction is attempted. Instead, the don't care bit positions of the substantially compacted vector are random filled (with 1s and 0s) and fault simulated, and a new test vector is generated.
An advantage of dynamic compaction, as is generally recognized, is that it usually results in a smaller set of test vectors than that achieved by static compaction. Reducing the set of the test vectors, correspondingly reduces time required to generate them. However, dynamic compaction is generally recognized as being computationally intensive. Indeed, since the publication of the Goel Paper, it has been generally accepted in the relevant industry that dynamic compaction achieves better results than static compaction, by reducing the total number of tests that need to be applied at a tester to a given DUT. Nevertheless, as integrated circuits continue to grow in size and complexity, even dynamic compaction techniques result in memory shortages and excessive computation problems, and therefore further improvements are desired.